Simulation Results: pwrmgr

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.85 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 96.87 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.870s 23.715us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.670s 47.252us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.720s 79.035us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.230s 70.377us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.880s 52.622us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 70.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.900s 159.363us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.900s 159.363us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.960s 39.401us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 45.640us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.760s 47.828us 1 1 100.00
pwrmgr_reset_invalid 0.790s 118.064us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.760s 47.828us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.410s 201.052us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.630s 72.679us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.650s 76.198us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.140s 467.426us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.840s 39.378us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.540s 175.132us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.540s 175.132us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 47.252us 1 1 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 70.377us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 126.084us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 47.252us 1 1 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
pwrmgr_csr_aliasing 1.230s 70.377us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 126.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.810s 7.878us 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.810s 7.878us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.980s 864.091us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.410s 201.052us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.040s 74.707us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 39.936us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.780s 30.780us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 72.653us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.780s 43.684us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.110s 441.925us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.940s 46.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.880s 356.484us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 1.500s 486.161us 1 1 100.00