Simulation Results: rom_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.51 %
  • code
  • 97.89 %
  • assert
  • 96.80 %
  • func
  • 97.85 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 99.95 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.660s 175.550us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.560s 544.705us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.990s 385.766us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.450s 140.619us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.460s 126.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.550s 139.141us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.990s 385.766us 1 1 100.00
rom_ctrl_csr_aliasing 3.460s 126.311us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.950s 372.455us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.180s 215.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.620s 1357.354us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.480s 602.440us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.660s 643.915us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.750s 243.444us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.250s 570.898us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.250s 570.898us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.560s 544.705us 1 1 100.00
rom_ctrl_csr_rw 2.990s 385.766us 1 1 100.00
rom_ctrl_csr_aliasing 3.460s 126.311us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.730s 299.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.560s 544.705us 1 1 100.00
rom_ctrl_csr_rw 2.990s 385.766us 1 1 100.00
rom_ctrl_csr_aliasing 3.460s 126.311us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.730s 299.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.690s 1483.843us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
rom_ctrl_tl_intg_err 40.550s 630.883us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.660s 175.550us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.660s 175.550us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.660s 175.550us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 40.550s 630.883us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
rom_ctrl_kmac_err_chk 5.660s 643.915us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 48.470s 3079.807us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.690s 1483.843us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.170s 1103.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 144.810s 2049.569us 1 1 100.00