Simulation Results: rom_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 96.52 %
  • assert
  • 95.49 %
  • func
  • 95.94 %
  • line
  • 99.32 %
  • branch
  • 97.81 %
  • cond
  • 93.02 %
  • toggle
  • 99.13 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.330s 9059.845us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.430s 943.638us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.060s 289.963us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.390s 208.051us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.500s 536.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.010s 213.272us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.060s 289.963us 1 1 100.00
rom_ctrl_csr_aliasing 6.500s 536.047us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.200s 1413.642us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.890s 290.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.500s 218.090us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.330s 859.165us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.940s 2645.837us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.320s 887.714us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.770s 306.969us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.770s 306.969us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.430s 943.638us 1 1 100.00
rom_ctrl_csr_rw 7.060s 289.963us 1 1 100.00
rom_ctrl_csr_aliasing 6.500s 536.047us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.170s 290.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.430s 943.638us 1 1 100.00
rom_ctrl_csr_rw 7.060s 289.963us 1 1 100.00
rom_ctrl_csr_aliasing 6.500s 536.047us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.170s 290.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.100s 761.220us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
rom_ctrl_tl_intg_err 93.580s 463.590us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.330s 9059.845us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.330s 9059.845us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.330s 9059.845us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 93.580s 463.590us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
rom_ctrl_kmac_err_chk 12.940s 2645.837us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.160s 2696.315us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.100s 761.220us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 440.500s 723.397us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 74.350s 2795.630us 1 1 100.00