Simulation Results: rstmgr

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.84 %
  • code
  • 99.28 %
  • assert
  • 97.72 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 256.206us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.910s 83.067us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.520s 275.068us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.920s 426.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.430s 192.778us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00
rstmgr_csr_aliasing 1.920s 426.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.970s 221.363us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.470s 139.331us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.190s 165.408us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.670s 1074.373us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.670s 1074.373us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.670s 1074.373us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.670s 1074.373us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.340s 4774.939us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.760s 82.655us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.170s 301.737us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.170s 301.737us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 83.067us 1 1 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00
rstmgr_csr_aliasing 1.920s 426.775us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 87.535us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.910s 83.067us 1 1 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00
rstmgr_csr_aliasing 1.920s 426.775us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 87.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.160s 8497.355us 1 1 100.00
rstmgr_tl_intg_err 1.960s 511.169us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.160s 8497.355us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.160s 8497.355us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.960s 511.169us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 183.445us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.290s 1971.964us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.020s 301.913us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.160s 8497.355us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 69.664us 1 1 100.00