Simulation Results: spi_device

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.99 %
  • code
  • 92.79 %
  • assert
  • 94.30 %
  • func
  • 64.88 %
  • line
  • 99.02 %
  • branch
  • 98.20 %
  • cond
  • 95.95 %
  • toggle
  • 83.54 %
  • FSM
  • 87.23 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 134.310s 24401.077us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.170s 396.001us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.470s 356.981us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.680s 613.890us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 13.190s 1284.628us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.580s 53.911us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.470s 356.981us 1 1 100.00
spi_device_csr_aliasing 13.190s 1284.628us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 31.414us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.430s 58.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.720s 20.186us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.660s 24.172us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.640s 7.012us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.990s 88.232us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.990s 88.232us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.790s 1527.727us 1 1 100.00
spi_device_tpm_sts_read 0.770s 92.101us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.780s 23355.470us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.930s 12052.737us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 3750.614us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.000s 3750.614us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.540s 920.466us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.540s 920.466us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.540s 920.466us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.540s 920.466us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.540s 920.466us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.980s 752.988us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.320s 4981.080us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.320s 4981.080us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.320s 4981.080us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.940s 196.339us 1 1 100.00
spi_device_read_buffer_direct 3.970s 646.642us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.320s 4981.080us 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 19.570s 19701.563us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.190s 1525.511us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.190s 1525.511us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 134.310s 24401.077us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 63.790s 7578.869us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 17.630s 6346.397us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 47.256us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.670s 15.118us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.270s 506.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.270s 506.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 396.001us 1 1 100.00
spi_device_csr_rw 1.470s 356.981us 1 1 100.00
spi_device_csr_aliasing 13.190s 1284.628us 1 1 100.00
spi_device_same_csr_outstanding 2.360s 2372.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 396.001us 1 1 100.00
spi_device_csr_rw 1.470s 356.981us 1 1 100.00
spi_device_csr_aliasing 13.190s 1284.628us 1 1 100.00
spi_device_same_csr_outstanding 2.360s 2372.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.020s 38.768us 1 1 100.00
spi_device_tl_intg_err 9.510s 560.950us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.510s 560.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 12.380s 894.895us 1 1 100.00