Simulation Results: spi_device

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.90 %
  • code
  • 94.22 %
  • assert
  • 94.27 %
  • func
  • 75.20 %
  • line
  • 99.14 %
  • branch
  • 98.40 %
  • cond
  • 96.46 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 26.890s 1845.672us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.930s 269.312us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.670s 71.870us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.050s 2697.365us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.590s 3641.023us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.990s 40.747us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.670s 71.870us 1 1 100.00
spi_device_csr_aliasing 15.590s 3641.023us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 41.968us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.020s 20.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.790s 73.929us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.900s 51.976us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.680s 16.333us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.710s 43.463us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.710s 43.463us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.890s 3897.366us 1 1 100.00
spi_device_tpm_sts_read 0.730s 170.470us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 13.360s 3196.465us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.470s 259.402us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.130s 2484.449us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.130s 2484.449us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.370s 1995.112us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.370s 1995.112us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.370s 1995.112us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.370s 1995.112us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.370s 1995.112us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.390s 739.188us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.700s 6596.087us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.700s 6596.087us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.700s 6596.087us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.840s 491.280us 1 1 100.00
spi_device_read_buffer_direct 6.910s 840.250us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 14.700s 6596.087us 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 141.580s 105450.291us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.270s 956.108us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.270s 956.108us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 26.890s 1845.672us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 33.900s 27823.263us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 146.580s 18866.623us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.640s 12.458us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.740s 27.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.380s 565.054us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.380s 565.054us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 269.312us 1 1 100.00
spi_device_csr_rw 1.670s 71.870us 1 1 100.00
spi_device_csr_aliasing 15.590s 3641.023us 1 1 100.00
spi_device_same_csr_outstanding 1.390s 27.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 269.312us 1 1 100.00
spi_device_csr_rw 1.670s 71.870us 1 1 100.00
spi_device_csr_aliasing 15.590s 3641.023us 1 1 100.00
spi_device_same_csr_outstanding 1.390s 27.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.940s 68.348us 1 1 100.00
spi_device_tl_intg_err 5.770s 1528.845us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.770s 1528.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 50.520s 17609.422us 1 1 100.00