Simulation Results: spi_host

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.30 %
  • code
  • 95.02 %
  • assert
  • 93.54 %
  • func
  • 88.33 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 5.000s 406.979us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 17.506us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 15.877us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 357.751us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 18.124us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 33.217us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 15.877us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.124us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 40.324us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 37.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 25.340us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 330.802us 1 1 100.00
spi_host_error_cmd 2.000s 45.051us 1 1 100.00
spi_host_event 7.000s 495.257us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 6.000s 551.392us 1 1 100.00
speed 1 1 100.00
spi_host_speed 6.000s 551.392us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 6.000s 551.392us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 8.000s 495.068us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 30.939us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 6.000s 551.392us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 6.000s 551.392us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 5.000s 406.979us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 5.000s 406.979us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 627.645us 1 1 100.00
spien 1 1 100.00
spi_host_spien 8.000s 2714.315us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 66.000s 4495.291us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 125.219us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 330.802us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 16.243us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 36.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 114.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 114.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 17.506us 1 1 100.00
spi_host_csr_rw 1.000s 15.877us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.124us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 49.157us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 17.506us 1 1 100.00
spi_host_csr_rw 1.000s 15.877us 1 1 100.00
spi_host_csr_aliasing 1.000s 18.124us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 49.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 220.855us 1 1 100.00
spi_host_tl_intg_err 1.000s 287.867us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 287.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 365.000s 21242.480us 1 1 100.00