Simulation Results: sram_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.87 %
  • code
  • 96.05 %
  • assert
  • 95.83 %
  • func
  • 95.73 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.41 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.320s 1546.975us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.800s 31.001us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.790s 10.801us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.720s 146.190us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 99.487us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.590s 3107.921us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.790s 10.801us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 99.487us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 214.230s 10722.459us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 124.050s 20473.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 354.160s 6799.310us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 186.910s 8871.756us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 594.540s 85822.248us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 618.380s 49466.887us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 41.920s 67265.752us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 480.440s 17431.040us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 9.650s 515.428us 1 1 100.00
sram_ctrl_partial_access_b2b 401.710s 43549.935us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.710s 1163.124us 1 1 100.00
sram_ctrl_throughput_w_partial_write 14.130s 785.288us 1 1 100.00
sram_ctrl_throughput_w_readback 54.210s 3626.866us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 253.930s 4699.171us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.080s 369.126us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2548.490s 27938.714us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.980s 48.102us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.330s 45.036us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.330s 45.036us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 31.001us 1 1 100.00
sram_ctrl_csr_rw 0.790s 10.801us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 99.487us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.980s 18.671us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 31.001us 1 1 100.00
sram_ctrl_csr_rw 0.790s 10.801us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 99.487us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.980s 18.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.520s 3727.219us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.340s 719.734us 1 1 100.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.340s 719.734us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 253.930s 4699.171us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 253.930s 4699.171us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.790s 10.801us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 480.440s 17431.040us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 480.440s 17431.040us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 480.440s 17431.040us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 41.920s 67265.752us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.330s 690.852us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.520s 3727.219us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.900s 689.852us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.320s 1546.975us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.320s 1546.975us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 480.440s 17431.040us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 41.920s 67265.752us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.320s 1546.975us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.850s 3.469us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 79.330s 9838.937us 1 1 100.00