Simulation Results: sram_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.10 %
  • code
  • 95.86 %
  • assert
  • 95.79 %
  • func
  • 96.66 %
  • line
  • 98.98 %
  • branch
  • 97.47 %
  • cond
  • 92.17 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.480s 51.487us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.840s 25.466us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.670s 17.283us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.380s 189.153us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 17.920us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.660s 114.561us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.670s 17.283us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 17.920us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.250s 5517.511us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.300s 106.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 267.110s 9013.328us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 222.550s 2903.213us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 11.390s 888.092us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 157.100s 1754.373us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.390s 1545.708us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 257.820s 14590.083us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.640s 273.804us 1 1 100.00
sram_ctrl_partial_access_b2b 313.900s 56016.264us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 61.740s 135.793us 1 1 100.00
sram_ctrl_throughput_w_partial_write 40.960s 347.811us 1 1 100.00
sram_ctrl_throughput_w_readback 52.600s 594.673us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 378.590s 6184.608us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 231.691us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1345.690s 218950.484us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.960s 40.404us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.690s 650.081us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.690s 650.081us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.840s 25.466us 1 1 100.00
sram_ctrl_csr_rw 0.670s 17.283us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 17.920us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.870s 37.214us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.840s 25.466us 1 1 100.00
sram_ctrl_csr_rw 0.670s 17.283us 1 1 100.00
sram_ctrl_csr_aliasing 0.810s 17.920us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.870s 37.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.670s 806.564us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.130s 537.275us 1 1 100.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.130s 537.275us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 378.590s 6184.608us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 378.590s 6184.608us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.670s 17.283us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 257.820s 14590.083us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 257.820s 14590.083us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 257.820s 14590.083us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.390s 1545.708us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 1.060s 30.275us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.670s 806.564us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.420s 414.659us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.480s 51.487us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.480s 51.487us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 257.820s 14590.083us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.390s 1545.708us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.480s 51.487us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.670s 1.590us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 126.980s 5136.354us 1 1 100.00