Simulation Results: sysrst_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.99 %
  • code
  • 92.94 %
  • assert
  • 93.77 %
  • func
  • 65.25 %
  • line
  • 97.34 %
  • branch
  • 97.48 %
  • cond
  • 94.87 %
  • toggle
  • 100.00 %
  • FSM
  • 75.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.770s 2117.667us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.100s 2448.502us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.760s 2274.388us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.530s 2344.213us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4043.453us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.180s 2070.805us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 99.130s 27480.408us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.910s 2300.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.480s 2235.569us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.180s 2070.805us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.910s 2300.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 282.720s 200154.645us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 134.230s 152375.447us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.770s 3335.406us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.780s 5786.657us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.870s 2511.066us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.170s 2059.467us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.280s 3859.566us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.830s 2621.621us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.440s 4567.255us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.330s 38318.911us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 4.840s 9133.652us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.340s 2014.401us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.550s 2017.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.620s 2022.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.620s 2022.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4043.453us 1 1 100.00
sysrst_ctrl_csr_rw 1.180s 2070.805us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.910s 2300.398us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.710s 4684.760us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4043.453us 1 1 100.00
sysrst_ctrl_csr_rw 1.180s 2070.805us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.910s 2300.398us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 12.710s 4684.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 41.900s 22011.064us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.770s 22295.027us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.770s 22295.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.840s 11228.112us 1 1 100.00