Simulation Results: uart

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.95 %
  • code
  • 96.65 %
  • assert
  • 97.12 %
  • func
  • 49.08 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.43 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 4.570s 5835.424us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.700s 30.081us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.720s 16.237us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.240s 118.056us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.920s 120.342us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.830s 98.171us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.720s 16.237us 1 1 100.00
uart_csr_aliasing 0.920s 120.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 40.050s 30152.082us 1 1 100.00
parity 2 2 100.00
uart_smoke 4.570s 5835.424us 1 1 100.00
uart_tx_rx 40.050s 30152.082us 1 1 100.00
parity_error 2 2 100.00
uart_intr 42.320s 33128.109us 1 1 100.00
uart_rx_parity_err 64.960s 308973.728us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 40.050s 30152.082us 1 1 100.00
uart_intr 42.320s 33128.109us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 50.200s 97775.122us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 28.750s 23332.048us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 15.150s 10461.090us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 42.320s 33128.109us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 42.320s 33128.109us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 42.320s 33128.109us 1 1 100.00
perf 1 1 100.00
uart_perf 16.460s 9152.593us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 12.310s 6655.581us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 12.310s 6655.581us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 9.190s 13607.198us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.500s 3488.633us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.310s 6272.502us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.670s 4106.377us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 568.050s 129447.483us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 10.070s 56691.344us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.550s 19.074us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.760s 51.753us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.130s 118.387us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.130s 118.387us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.700s 30.081us 1 1 100.00
uart_csr_rw 0.720s 16.237us 1 1 100.00
uart_csr_aliasing 0.920s 120.342us 1 1 100.00
uart_same_csr_outstanding 0.710s 21.349us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.700s 30.081us 1 1 100.00
uart_csr_rw 0.720s 16.237us 1 1 100.00
uart_csr_aliasing 0.920s 120.342us 1 1 100.00
uart_same_csr_outstanding 0.710s 21.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 0.980s 250.154us 1 1 100.00
uart_sec_cm 0.870s 176.411us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.980s 250.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 13.250s 12871.758us 1 1 100.00