Simulation Results: adc_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.28 %
  • code
  • 97.55 %
  • assert
  • 95.62 %
  • func
  • 41.67 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 95.45 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.660s 6051.335us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.520s 632.585us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.890s 519.233us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 17.240s 10321.754us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.370s 638.632us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.920s 651.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.890s 519.233us 1 1 100.00
adc_ctrl_csr_aliasing 2.370s 638.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 398.730s 487689.962us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 220.520s 159252.131us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 565.620s 324170.019us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 117.870s 494516.734us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 79.570s 187041.808us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 156.810s 199607.580us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 206.860s 492908.090us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 38.020s 170853.348us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.500s 4577.686us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 39.150s 23583.233us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 48.770s 132264.441us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 91.180s 52910.458us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.010s 292.059us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.940s 293.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.020s 580.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.020s 580.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.520s 632.585us 1 1 100.00
adc_ctrl_csr_rw 0.890s 519.233us 1 1 100.00
adc_ctrl_csr_aliasing 2.370s 638.632us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.500s 4556.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.520s 632.585us 1 1 100.00
adc_ctrl_csr_rw 0.890s 519.233us 1 1 100.00
adc_ctrl_csr_aliasing 2.370s 638.632us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.500s 4556.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.380s 4281.135us 1 1 100.00
adc_ctrl_tl_intg_err 3.600s 4578.744us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.600s 4578.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 8.290s 3522.257us 1 1 100.00