| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.790s | 25.772us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.690s | 16.745us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| clkmgr_csr_bit_bash | 2.750s | 222.927us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 1.100s | 126.799us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 1.210s | 58.588us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.100s | 126.799us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.670s | 20.306us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.710s | 30.698us | 1 | 1 | 100.00 | |
| extclk | 1 | 1 | 100.00 | |||
| clkmgr_extclk | 0.870s | 92.371us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.690s | 17.764us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.790s | 25.772us | 1 | 1 | 100.00 | |
| frequency | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 6.790s | 2478.536us | 1 | 1 | 100.00 | |
| frequency_timeout | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 7.520s | 1696.895us | 1 | 1 | 100.00 | |
| frequency_overflow | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 6.790s | 2478.536us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| clkmgr_stress_all | 4.880s | 1586.233us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.740s | 63.499us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.230s | 29.271us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.230s | 29.271us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.690s | 16.745us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.100s | 126.799us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 0.860s | 45.604us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.690s | 16.745us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.100s | 126.799us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 0.860s | 45.604us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| clkmgr_sec_cm | 1.700s | 277.516us | 1 | 1 | 100.00 | |
| clkmgr_tl_intg_err | 1.240s | 71.345us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.250s | 146.805us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.250s | 146.805us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.250s | 146.805us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.250s | 146.805us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 1.740s | 97.049us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| clkmgr_tl_intg_err | 1.240s | 71.345us | 1 | 1 | 100.00 | |
| sec_cm_meas_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 6.790s | 2478.536us | 1 | 1 | 100.00 | |
| sec_cm_timeout_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 7.520s | 1696.895us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.250s | 146.805us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_idle_intersig_mubi | 0.780s | 31.207us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.700s | 18.071us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 0.770s | 24.130us | 1 | 1 | 100.00 | |
| sec_cm_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 1.110s | 235.694us | 1 | 1 | 100.00 | |
| sec_cm_div_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_div_intersig_mubi | 0.760s | 41.494us | 1 | 1 | 100.00 | |
| sec_cm_jitter_config_mubi | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| sec_cm_idle_ctr_redun | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.700s | 277.516us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| sec_cm_clk_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.870s | 121.878us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.700s | 277.516us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 1 | 1 | 100.00 | |||
| clkmgr_regwen | 3.190s | 1177.213us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_stress_all_with_rand_reset | 83.170s | 24459.117us | 1 | 1 | 100.00 | |