Simulation Results: edn

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.01 %
  • code
  • 78.94 %
  • assert
  • 94.89 %
  • func
  • 75.19 %
  • line
  • 97.17 %
  • branch
  • 89.74 %
  • cond
  • 84.44 %
  • toggle
  • 75.68 %
  • FSM
  • 47.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 37.488us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 62.559us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 21.600us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.470s 44.377us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.920s 38.558us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.100s 34.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 21.600us 1 1 100.00
edn_csr_aliasing 0.920s 38.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.070s 135.276us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.070s 135.276us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.070s 135.276us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 20.781us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 23.481us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 23.011us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 13.005us 1 1 100.00
edn_disable_auto_req_mode 0.990s 88.995us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.550s 243.634us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.870s 17.849us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 61.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.730s 247.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.730s 247.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 62.559us 1 1 100.00
edn_csr_rw 0.780s 21.600us 1 1 100.00
edn_csr_aliasing 0.920s 38.558us 1 1 100.00
edn_same_csr_outstanding 0.810s 40.404us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 62.559us 1 1 100.00
edn_csr_rw 0.780s 21.600us 1 1 100.00
edn_csr_aliasing 0.920s 38.558us 1 1 100.00
edn_same_csr_outstanding 0.810s 40.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
edn_tl_intg_err 1.260s 95.473us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 44.282us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 23.481us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 23.481us 1 1 100.00
edn_sec_cm 7.600s 721.581us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 23.481us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.260s 95.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.960s 2013.602us 1 1 100.00