Simulation Results: flash_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.26 %
  • assert
  • 96.62 %
  • func
  • 95.54 %
  • line
  • 95.98 %
  • branch
  • 97.17 %
  • cond
  • 93.48 %
  • toggle
  • 98.27 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 38.230s 84.410us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.110s 23.309us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.820s 35.153us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 24.960s 1341.668us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 33.630s 8184.850us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.340s 326.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
flash_ctrl_csr_aliasing 33.630s 8184.850us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.230s 58.011us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.760s 102.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 17.440s 97.088us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 31.350s 221.735us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1261.440s 340219.817us 1 1 100.00
flash_ctrl_hw_rma_reset 744.980s 540361.588us 1 1 100.00
flash_ctrl_lcmgr_intg 5.360s 39.735us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1162.910s 392368.479us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 147.680s 5802.741us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.880s 77.890us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2880.930s 49898.664us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 48.050s 1514.283us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.040s 82.630us 1 1 100.00
flash_ctrl_rw_evict_all_en 18.530s 42.580us 1 1 100.00
flash_ctrl_re_evict 16.000s 126.612us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 49.180s 205.778us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 49.180s 205.778us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 230.490s 54750.949us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.540s 303.304us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 157.490s 745.091us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 548.490s 5669.546us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 307.230s 1470.974us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 949.630s 2174.813us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.990s 24.697us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 134.590s 1517.320us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 14.440s 19.436us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.320s 29.642us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 136.700s 100.615us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 26.750s 1225.531us 1 1 100.00
flash_ctrl_otp_reset 50.180s 607.788us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1261.440s 340219.817us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 99.870s 1497.970us 0 1 0.00
flash_ctrl_intr_wr 38.780s 2262.236us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 292.150s 46207.738us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 123.620s 40303.236us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 52.610s 1197.154us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.560s 2678.113us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 8.890s 26.183us 1 1 100.00
flash_ctrl_ro_derr 89.450s 1485.130us 1 1 100.00
flash_ctrl_rw_derr 150.400s 3718.038us 1 1 100.00
flash_ctrl_derr_detect 106.290s 2909.505us 1 1 100.00
flash_ctrl_integrity 334.750s 11585.969us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.030s 68.618us 1 1 100.00
flash_ctrl_ro_serr 96.290s 1319.213us 1 1 100.00
flash_ctrl_rw_serr 110.850s 3726.705us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 52.420s 3845.183us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 48.230s 1378.811us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 128.510s 2154.829us 1 1 100.00
flash_ctrl_write_word_sweep 6.770s 157.850us 1 1 100.00
flash_ctrl_read_word_sweep 6.090s 26.841us 1 1 100.00
flash_ctrl_ro 76.660s 2436.469us 1 1 100.00
flash_ctrl_rw 333.860s 61615.973us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.670s 1250.858us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 588.550s 166587.693us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.660s 10107.007us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.970s 24.134us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.450s 30.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.710s 40.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.710s 40.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.820s 35.153us 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
flash_ctrl_csr_aliasing 33.630s 8184.850us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.900s 40.185us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.820s 35.153us 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
flash_ctrl_csr_aliasing 33.630s 8184.850us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.900s 40.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 32.230s 323.576us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 184.970s 962.392us 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 184.970s 962.392us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 184.970s 962.392us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.860s 69.863us 1 1 100.00
flash_ctrl_wr_intg 6.270s 374.454us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 38.230s 84.410us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.180s 607.788us 1 1 100.00
flash_ctrl_disable 14.440s 19.436us 1 1 100.00
flash_ctrl_sec_info_access 38.510s 3909.279us 1 1 100.00
flash_ctrl_connect 7.320s 29.642us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.810s 39.889us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.780s 28.818us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.560s 29.484us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 14.440s 19.436us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.860s 69.863us 1 1 100.00
flash_ctrl_access_after_disable 7.900s 84.188us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.140s 38.449us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 14.440s 19.436us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.540s 303.304us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 333.860s 61615.973us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 110.850s 3726.705us 1 1 100.00
flash_ctrl_rw_derr 150.400s 3718.038us 1 1 100.00
flash_ctrl_integrity 334.750s 11585.969us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1261.440s 340219.817us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.690s 913.880us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.580s 22.903us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.760s 22.570us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1543.490s 863.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.950s 80.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 94.880s 164.495us 1 1 100.00