Simulation Results: hmac

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.79 %
  • code
  • 97.93 %
  • assert
  • 96.42 %
  • func
  • 45.03 %
  • line
  • 99.68 %
  • branch
  • 99.34 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.200s 412.935us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.780s 38.444us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.770s 18.662us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.720s 8291.928us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.500s 907.041us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.870s 18.315us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.770s 18.662us 1 1 100.00
hmac_csr_aliasing 4.500s 907.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 54.640s 56542.544us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 14.950s 358.008us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.650s 2998.371us 1 1 100.00
hmac_test_sha384_vectors 23.650s 519.440us 1 1 100.00
hmac_test_sha512_vectors 20.610s 236.063us 1 1 100.00
hmac_test_hmac256_vectors 11.160s 243.534us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 379.932us 1 1 100.00
hmac_test_hmac512_vectors 11.130s 2227.190us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.070s 853.053us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 850.240s 5613.814us 1 1 100.00
error 1 1 100.00
hmac_error 58.530s 4455.461us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 44.560s 19603.188us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.200s 412.935us 1 1 100.00
hmac_long_msg 54.640s 56542.544us 1 1 100.00
hmac_back_pressure 14.950s 358.008us 1 1 100.00
hmac_datapath_stress 850.240s 5613.814us 1 1 100.00
hmac_burst_wr 6.070s 853.053us 1 1 100.00
hmac_stress_all 1007.720s 41537.180us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.200s 412.935us 1 1 100.00
hmac_long_msg 54.640s 56542.544us 1 1 100.00
hmac_back_pressure 14.950s 358.008us 1 1 100.00
hmac_datapath_stress 850.240s 5613.814us 1 1 100.00
hmac_wipe_secret 44.560s 19603.188us 1 1 100.00
hmac_test_sha256_vectors 10.650s 2998.371us 1 1 100.00
hmac_test_sha384_vectors 23.650s 519.440us 1 1 100.00
hmac_test_sha512_vectors 20.610s 236.063us 1 1 100.00
hmac_test_hmac256_vectors 11.160s 243.534us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 379.932us 1 1 100.00
hmac_test_hmac512_vectors 11.130s 2227.190us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.200s 412.935us 1 1 100.00
hmac_long_msg 54.640s 56542.544us 1 1 100.00
hmac_back_pressure 14.950s 358.008us 1 1 100.00
hmac_datapath_stress 850.240s 5613.814us 1 1 100.00
hmac_burst_wr 6.070s 853.053us 1 1 100.00
hmac_error 58.530s 4455.461us 1 1 100.00
hmac_wipe_secret 44.560s 19603.188us 1 1 100.00
hmac_test_sha256_vectors 10.650s 2998.371us 1 1 100.00
hmac_test_sha384_vectors 23.650s 519.440us 1 1 100.00
hmac_test_sha512_vectors 20.610s 236.063us 1 1 100.00
hmac_test_hmac256_vectors 11.160s 243.534us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 379.932us 1 1 100.00
hmac_test_hmac512_vectors 11.130s 2227.190us 1 1 100.00
hmac_stress_all 1007.720s 41537.180us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1007.720s 41537.180us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.780s 30.924us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.760s 21.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.700s 80.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.700s 80.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.780s 38.444us 1 1 100.00
hmac_csr_rw 0.770s 18.662us 1 1 100.00
hmac_csr_aliasing 4.500s 907.041us 1 1 100.00
hmac_same_csr_outstanding 2.140s 1809.315us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.780s 38.444us 1 1 100.00
hmac_csr_rw 0.770s 18.662us 1 1 100.00
hmac_csr_aliasing 4.500s 907.041us 1 1 100.00
hmac_same_csr_outstanding 2.140s 1809.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.540s 94.744us 1 1 100.00
hmac_sec_cm 1.380s 101.862us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.540s 94.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.200s 412.935us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.200s 556.721us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 230.780s 26504.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.940s 44.470us 1 1 100.00