Simulation Results: lc_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 85.02 %
  • assert
  • 94.13 %
  • func
  • 91.64 %
  • line
  • 97.13 %
  • branch
  • 93.82 %
  • cond
  • 79.45 %
  • toggle
  • 81.28 %
  • FSM
  • 73.40 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.460s 93.809us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.170s 63.842us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.180s 23.551us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.540s 37.678us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 151.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.660s 22.228us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.180s 23.551us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 151.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.650s 55.085us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.160s 3947.910us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 21.803us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.870s 64.288us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.860s 549.518us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_prog_failure 2.870s 64.288us 1 1 100.00
lc_ctrl_errors 6.860s 549.518us 1 1 100.00
lc_ctrl_security_escalation 4.800s 320.118us 1 1 100.00
lc_ctrl_jtag_state_failure 8.460s 338.857us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.620s 131.007us 1 1 100.00
lc_ctrl_jtag_errors 44.670s 18139.757us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 3.060s 118.498us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.050s 137.654us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.250s 878.838us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.590s 569.620us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.820s 244.198us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.790s 57.145us 1 1 100.00
lc_ctrl_jtag_alert_test 1.390s 24.529us 1 1 100.00
lc_ctrl_jtag_smoke 2.070s 232.901us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.630s 2840.375us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.620s 131.007us 1 1 100.00
lc_ctrl_jtag_errors 44.670s 18139.757us 1 1 100.00
lc_ctrl_jtag_access 2.500s 1085.351us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.500s 1135.050us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.770s 1129.443us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.230s 26.765us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 12.000s 2264.675us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 58.874us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 751.961us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 751.961us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 63.842us 1 1 100.00
lc_ctrl_csr_rw 1.180s 23.551us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 151.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 142.183us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 63.842us 1 1 100.00
lc_ctrl_csr_rw 1.180s 23.551us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 151.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 142.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.660s 166.308us 1 1 100.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.660s 166.308us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.160s 3947.910us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.990s 20.579us 0 1 0.00
lc_ctrl_sec_cm 6.270s 554.402us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.800s 320.118us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.650s 55.085us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.630s 2840.375us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.720s 1764.928us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.720s 1764.928us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.600s 188.909us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.850s 1550.692us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.850s 1550.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.320s 221.601us 0 1 0.00