Simulation Results: lc_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.63 %
  • code
  • 84.25 %
  • assert
  • 94.13 %
  • func
  • 84.52 %
  • line
  • 96.97 %
  • branch
  • 93.62 %
  • cond
  • 79.35 %
  • toggle
  • 80.80 %
  • FSM
  • 70.53 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.510s 114.914us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 18.955us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.900s 46.241us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.560s 110.745us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 52.798us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.200s 33.891us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.900s 46.241us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 52.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.330s 69.979us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.400s 904.872us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.090s 25.370us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.120s 284.609us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.270s 1177.464us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_prog_failure 2.120s 284.609us 1 1 100.00
lc_ctrl_errors 7.270s 1177.464us 1 1 100.00
lc_ctrl_security_escalation 5.700s 400.317us 1 1 100.00
lc_ctrl_jtag_state_failure 2.300s 96.792us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.900s 807.116us 1 1 100.00
lc_ctrl_jtag_errors 57.100s 6483.403us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 3.710s 630.464us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.740s 60.038us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.900s 807.116us 1 1 100.00
lc_ctrl_jtag_errors 57.100s 6483.403us 1 1 100.00
lc_ctrl_jtag_access 3.390s 148.578us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.000s 972.757us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.770s 172.032us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.560s 52.899us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.960s 3006.034us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.320s 397.826us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 45.310us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.100s 314.610us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 114.207us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.410s 2472.042us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 25.883us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 4.170s 137.772us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.880s 19.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.170s 333.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.170s 333.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 18.955us 1 1 100.00
lc_ctrl_csr_rw 0.900s 46.241us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 52.798us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 73.955us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 18.955us 1 1 100.00
lc_ctrl_csr_rw 0.900s 46.241us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 52.798us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 73.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
lc_ctrl_tl_intg_err 2.900s 251.984us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.900s 251.984us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.400s 904.872us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.260s 156.562us 0 1 0.00
lc_ctrl_sec_cm 7.890s 268.076us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.700s 400.317us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.330s 69.979us 0 1 0.00
lc_ctrl_jtag_state_post_trans 1.740s 60.038us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.270s 271.934us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.270s 271.934us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.880s 1836.548us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.760s 278.829us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.760s 278.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 28.070s 5787.211us 0 1 0.00