Simulation Results: pattgen

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 51.973us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 14.789us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 13.898us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 64.733us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 88.765us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 35.273us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 13.898us 1 1 100.00
pattgen_csr_aliasing 2.000s 88.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 380.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 65.000s 2745.361us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 67.703us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 536.000s 186548.654us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 14.047us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 13.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 110.232us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 110.232us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.789us 1 1 100.00
pattgen_csr_rw 1.000s 13.898us 1 1 100.00
pattgen_csr_aliasing 2.000s 88.765us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 83.560us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.789us 1 1 100.00
pattgen_csr_rw 1.000s 13.898us 1 1 100.00
pattgen_csr_aliasing 2.000s 88.765us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 83.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 165.349us 1 1 100.00
pattgen_tl_intg_err 2.000s 46.542us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 46.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 30.000s 7288.117us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 70.000s 10014.144us 0 1 0.00