Simulation Results: pwrmgr

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.85 %
  • code
  • 94.60 %
  • assert
  • 96.08 %
  • func
  • 96.87 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 25.735us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.700s 46.051us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.440s 287.883us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.800s 28.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.740s 46.038us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 28.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.970s 234.177us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.970s 234.177us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.960s 119.823us 1 1 100.00
pwrmgr_lowpower_invalid 0.720s 39.718us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.690s 82.526us 1 1 100.00
pwrmgr_reset_invalid 0.790s 146.328us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.690s 82.526us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.850s 337.545us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.590s 34.883us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.050s 144.342us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.530s 1962.340us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 37.412us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.100s 1249.211us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.100s 1249.211us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 46.051us 1 1 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 28.359us 1 1 100.00
pwrmgr_same_csr_outstanding 0.810s 20.852us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 46.051us 1 1 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
pwrmgr_csr_aliasing 0.800s 28.359us 1 1 100.00
pwrmgr_same_csr_outstanding 0.810s 20.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
pwrmgr_tl_intg_err 0.640s 8.119us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.640s 8.119us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.760s 928.080us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.850s 337.545us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.930s 65.544us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.660s 28.945us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.680s 6.629us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.560s 110.243us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.690s 60.986us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.080s 324.902us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 28.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.690s 341.637us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.150s 5527.237us 1 1 100.00