Simulation Results: rom_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.41 %
  • code
  • 98.50 %
  • assert
  • 95.49 %
  • func
  • 95.23 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 95.10 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.760s 202.466us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.910s 223.395us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.070s 212.655us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.740s 293.208us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 581.289us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.890s 566.338us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.070s 212.655us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 581.289us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.100s 212.099us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.380s 533.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.840s 178.590us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.940s 2895.410us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.230s 318.600us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.160s 385.653us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.860s 287.214us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.860s 287.214us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.910s 223.395us 1 1 100.00
rom_ctrl_csr_rw 3.070s 212.655us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 581.289us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.180s 187.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.910s 223.395us 1 1 100.00
rom_ctrl_csr_rw 3.070s 212.655us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 581.289us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.180s 187.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.170s 670.844us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
rom_ctrl_tl_intg_err 23.760s 633.611us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.760s 202.466us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.760s 202.466us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.760s 202.466us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.760s 633.611us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
rom_ctrl_kmac_err_chk 7.230s 318.600us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 67.990s 4613.921us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.170s 670.844us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 99.500s 1007.903us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 361.000s 18769.840us 1 1 100.00