Simulation Results: rom_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.39 %
  • code
  • 97.99 %
  • assert
  • 95.49 %
  • func
  • 95.70 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.46 %
  • toggle
  • 98.83 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.040s 1103.762us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.570s 296.536us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.680s 728.497us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.160s 545.729us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.070s 213.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.780s 589.175us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.680s 728.497us 1 1 100.00
rom_ctrl_csr_aliasing 6.070s 213.192us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.360s 1869.586us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.050s 287.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.630s 405.131us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 27.330s 5658.967us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.020s 2025.721us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.860s 376.916us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.460s 535.058us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.460s 535.058us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.570s 296.536us 1 1 100.00
rom_ctrl_csr_rw 5.680s 728.497us 1 1 100.00
rom_ctrl_csr_aliasing 6.070s 213.192us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.390s 288.796us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.570s 296.536us 1 1 100.00
rom_ctrl_csr_rw 5.680s 728.497us 1 1 100.00
rom_ctrl_csr_aliasing 6.070s 213.192us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.390s 288.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.960s 4501.756us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
rom_ctrl_tl_intg_err 50.720s 3122.249us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.040s 1103.762us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.040s 1103.762us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.040s 1103.762us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.720s 3122.249us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
rom_ctrl_kmac_err_chk 14.020s 2025.721us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 175.590s 24259.285us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.960s 4501.756us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 238.250s 1043.613us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 342.730s 10048.924us 1 1 100.00