Simulation Results: rstmgr

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 99.16 %
  • assert
  • 97.32 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 98.74 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.370s 254.690us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.120s 123.898us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.080s 488.697us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.520s 163.658us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.350s 112.319us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00
rstmgr_csr_aliasing 1.520s 163.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.970s 131.156us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.320s 124.860us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.220s 184.193us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.740s 1618.624us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.740s 1618.624us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.740s 1618.624us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.740s 1618.624us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.080s 4322.821us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.680s 74.696us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.720s 116.611us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.720s 116.611us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 123.898us 1 1 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00
rstmgr_csr_aliasing 1.520s 163.658us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 77.371us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 123.898us 1 1 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00
rstmgr_csr_aliasing 1.520s 163.658us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 77.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 1.890s 480.210us 1 1 100.00
rstmgr_sec_cm 11.110s 9089.891us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.110s 9089.891us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.110s 9089.891us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.890s 480.210us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.080s 173.900us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.220s 1264.712us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.100s 302.780us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.110s 9089.891us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 81.123us 1 1 100.00