| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
66.67% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 0.900s | 692.775us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 13.681us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.610s | 22.283us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.780s | 249.957us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.670s | 27.469us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.740s | 137.788us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.610s | 22.283us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.670s | 27.469us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.660s | 152.735us | 0 | 1 | 0.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 0.900s | 1121.911us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 64.220s | 191077.919us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 64.220s | 191077.919us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 2.190s | 3112.856us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.490s | 20.445us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.600s | 18.552us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.180s | 610.066us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 2.180s | 610.066us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 13.681us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.610s | 22.283us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.670s | 27.469us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.650s | 47.878us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.640s | 13.681us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.610s | 22.283us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.670s | 27.469us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.650s | 47.878us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 0.740s | 65.436us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 0.950s | 99.492us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 0.950s | 99.492us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 1 | 100.00 | |||
| rv_timer_min | 0.520s | 43.534us | 1 | 1 | 100.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 1.050s | 413.538us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 30.880s | 3943.745us | 1 | 1 | 100.00 | |