Simulation Results: spi_device

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.92 %
  • code
  • 93.33 %
  • assert
  • 86.87 %
  • func
  • 68.55 %
  • line
  • 99.11 %
  • branch
  • 98.39 %
  • cond
  • 96.27 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 45.720s 27834.303us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.830s 83.587us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.410s 104.232us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.760s 527.755us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.560s 2669.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.840s 262.824us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.410s 104.232us 1 1 100.00
spi_device_csr_aliasing 10.560s 2669.175us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 12.881us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.000s 64.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.790s 117.522us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.740s 1.186us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.640s 6.264us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 7.420s 354.197us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 7.420s 354.197us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.640s 1424.327us 1 1 100.00
spi_device_tpm_sts_read 0.880s 311.964us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.120s 11976.897us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 15.730s 36099.777us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.680s 378.705us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.680s 378.705us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.770s 517.077us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.770s 517.077us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.770s 517.077us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.770s 517.077us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.770s 517.077us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.840s 1601.893us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.400s 1213.843us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.400s 1213.843us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.400s 1213.843us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.780s 547.540us 1 1 100.00
spi_device_read_buffer_direct 4.450s 2630.152us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.400s 1213.843us 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 88.560s 25251.168us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.870s 37.071us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.870s 37.071us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 45.720s 27834.303us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 71.330s 31678.341us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 33.980s 2785.150us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.700s 52.440us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 16.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.700s 61.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.700s 61.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 83.587us 1 1 100.00
spi_device_csr_rw 1.410s 104.232us 1 1 100.00
spi_device_csr_aliasing 10.560s 2669.175us 1 1 100.00
spi_device_same_csr_outstanding 3.160s 63.445us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 83.587us 1 1 100.00
spi_device_csr_rw 1.410s 104.232us 1 1 100.00
spi_device_csr_aliasing 10.560s 2669.175us 1 1 100.00
spi_device_same_csr_outstanding 3.160s 63.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 5.100s 574.872us 1 1 100.00
spi_device_sec_cm 1.260s 256.152us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.100s 574.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 356.880s 328173.642us 1 1 100.00