Simulation Results: spi_host

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.31 %
  • code
  • 94.63 %
  • assert
  • 93.54 %
  • func
  • 88.75 %
  • block
  • 96.40 %
  • line
  • 98.07 %
  • branch
  • 92.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 10.000s 2430.933us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.066us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 21.903us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 160.033us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 37.659us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 21.972us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 21.903us 1 1 100.00
spi_host_csr_aliasing 1.000s 37.659us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 7.000s 15.009us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 22.867us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 57.299us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 126.701us 1 1 100.00
spi_host_error_cmd 2.000s 20.005us 1 1 100.00
spi_host_event 9.000s 385.970us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 85.529us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 85.529us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 85.529us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 482.479us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 25.925us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 85.529us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 85.529us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 10.000s 2430.933us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 10.000s 2430.933us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 675.825us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 509.540us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 67.000s 10217.127us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 67.938us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 126.701us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 81.354us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 7.000s 16.547us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 9.000s 72.774us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 9.000s 72.774us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.066us 1 1 100.00
spi_host_csr_rw 1.000s 21.903us 1 1 100.00
spi_host_csr_aliasing 1.000s 37.659us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 17.382us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.066us 1 1 100.00
spi_host_csr_rw 1.000s 21.903us 1 1 100.00
spi_host_csr_aliasing 1.000s 37.659us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 17.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 8.000s 482.655us 1 1 100.00
spi_host_sec_cm 1.000s 329.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 8.000s 482.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 33.000s 3290.725us 1 1 100.00