Simulation Results: sram_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.08 %
  • code
  • 90.40 %
  • assert
  • 95.55 %
  • func
  • 96.29 %
  • line
  • 97.77 %
  • branch
  • 95.79 %
  • cond
  • 91.55 %
  • toggle
  • 90.71 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.840s 825.164us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.760s 14.239us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.780s 30.519us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.560s 124.480us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.540s 4348.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.780s 30.519us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.541us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 120.740s 35680.708us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 115.220s 37587.899us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 78.160s 10816.002us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 73.360s 1376.421us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1182.220s 644208.890us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 263.380s 8586.702us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 43.380s 156638.249us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 300.050s 31548.511us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 25.320s 1769.271us 1 1 100.00
sram_ctrl_partial_access_b2b 481.380s 33698.036us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 24.890s 953.082us 1 1 100.00
sram_ctrl_throughput_w_partial_write 14.660s 3114.300us 1 1 100.00
sram_ctrl_throughput_w_readback 43.590s 3643.953us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 286.710s 11801.593us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.580s 693.982us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 4031.340s 363704.702us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.870s 42.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.040s 153.615us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.040s 153.615us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 14.239us 1 1 100.00
sram_ctrl_csr_rw 0.780s 30.519us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.541us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 22.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 14.239us 1 1 100.00
sram_ctrl_csr_rw 0.780s 30.519us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 15.541us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 22.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.740s 15331.808us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
sram_ctrl_tl_intg_err 1.840s 363.286us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.840s 363.286us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 286.710s 11801.593us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 286.710s 11801.593us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.780s 30.519us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 300.050s 31548.511us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 300.050s 31548.511us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 300.050s 31548.511us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 43.380s 156638.249us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.440s 696.244us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.740s 15331.808us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.760s 676.155us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.840s 825.164us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.840s 825.164us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 300.050s 31548.511us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 43.380s 156638.249us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.840s 825.164us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.920s 14.134us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.740s 775.231us 1 1 100.00