Simulation Results: sram_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.31 %
  • code
  • 95.85 %
  • assert
  • 95.65 %
  • func
  • 94.43 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.04 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
90.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.670s 409.386us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.800s 55.290us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.850s 26.266us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.400s 44.911us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 45.955us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.930s 22.305us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.850s 26.266us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 45.955us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.240s 2330.367us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.270s 1106.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 561.590s 3030.511us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 143.080s 8333.217us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 50.150s 3421.433us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 170.330s 6940.116us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.090s 2541.377us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 892.860s 22940.101us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 10.810s 558.895us 1 1 100.00
sram_ctrl_partial_access_b2b 276.710s 5102.047us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 12.020s 95.417us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.220s 212.088us 1 1 100.00
sram_ctrl_throughput_w_readback 7.570s 440.118us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 525.490s 10566.489us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.830s 81.103us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1736.420s 290001.177us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.640s 21.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.470s 69.315us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.470s 69.315us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 55.290us 1 1 100.00
sram_ctrl_csr_rw 0.850s 26.266us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 45.955us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 52.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 55.290us 1 1 100.00
sram_ctrl_csr_rw 0.850s 26.266us 1 1 100.00
sram_ctrl_csr_aliasing 0.700s 45.955us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 52.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.780s 3869.829us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
sram_ctrl_tl_intg_err 1.250s 119.076us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.250s 119.076us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 525.490s 10566.489us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 525.490s 10566.489us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.850s 26.266us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 892.860s 22940.101us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 892.860s 22940.101us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 892.860s 22940.101us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.090s 2541.377us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.200s 63.732us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.780s 3869.829us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.990s 34.647us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.670s 409.386us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.670s 409.386us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 892.860s 22940.101us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.090s 2541.377us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.670s 409.386us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 17.910us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.210s 1244.567us 1 1 100.00