Simulation Results: sysrst_ctrl

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.32 %
  • code
  • 94.26 %
  • assert
  • 95.69 %
  • func
  • 63.02 %
  • line
  • 98.16 %
  • branch
  • 98.03 %
  • cond
  • 94.59 %
  • toggle
  • 99.77 %
  • FSM
  • 80.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.160s 2107.686us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.450s 2473.864us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.630s 2205.311us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.450s 2279.673us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.290s 4105.750us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 0.950s 2489.175us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 243.640s 75981.761us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2683.396us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.740s 2061.924us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 0.950s 2489.175us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2683.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 57.310s 128409.598us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 20.200s 41464.921us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.450s 3491.326us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.680s 2599.240us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.000s 2511.272us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.030s 2186.153us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.810s 2752.629us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.330s 2612.219us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.030s 5205.269us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 69.740s 39119.347us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.740s 6774.032us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.930s 2009.338us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.480s 2024.183us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.000s 2083.233us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.000s 2083.233us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.290s 4105.750us 1 1 100.00
sysrst_ctrl_csr_rw 0.950s 2489.175us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2683.396us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.070s 8065.532us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.290s 4105.750us 1 1 100.00
sysrst_ctrl_csr_rw 0.950s 2489.175us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2683.396us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.070s 8065.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 37.900s 22011.615us 1 1 100.00
sysrst_ctrl_tl_intg_err 78.210s 42498.128us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 78.210s 42498.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.570s 12608.986us 1 1 100.00