Simulation Results: uart

 
03/12/2025 17:57:19 sha: a5eb48e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.19 %
  • code
  • 95.84 %
  • assert
  • 97.12 %
  • func
  • 44.59 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.350s 668.238us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.870s 14.376us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.600s 13.871us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.010s 604.785us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.880s 14.758us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.850s 28.070us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.600s 13.871us 1 1 100.00
uart_csr_aliasing 0.880s 14.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 71.640s 72244.521us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.350s 668.238us 1 1 100.00
uart_tx_rx 71.640s 72244.521us 1 1 100.00
parity_error 2 2 100.00
uart_intr 21.730s 34449.230us 1 1 100.00
uart_rx_parity_err 175.010s 133112.397us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 71.640s 72244.521us 1 1 100.00
uart_intr 21.730s 34449.230us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 108.200s 108461.265us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 48.780s 155084.577us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 28.010s 189281.150us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 21.730s 34449.230us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 21.730s 34449.230us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 21.730s 34449.230us 1 1 100.00
perf 1 1 100.00
uart_perf 169.090s 19576.809us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.740s 1307.141us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.740s 1307.141us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 12.510s 37930.699us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.340s 4368.189us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 12.580s 7151.613us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 19.300s 6349.909us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 49.760s 83881.707us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 3.130s 18806.782us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.660s 14.353us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.780s 14.879us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.420s 80.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.420s 80.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.870s 14.376us 1 1 100.00
uart_csr_rw 0.600s 13.871us 1 1 100.00
uart_csr_aliasing 0.880s 14.758us 1 1 100.00
uart_same_csr_outstanding 0.770s 37.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.870s 14.376us 1 1 100.00
uart_csr_rw 0.600s 13.871us 1 1 100.00
uart_csr_aliasing 0.880s 14.758us 1 1 100.00
uart_same_csr_outstanding 0.770s 37.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.940s 201.778us 1 1 100.00
uart_tl_intg_err 1.270s 183.894us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.270s 183.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 25.780s 38260.483us 0 1 0.00