Simulation Results: adc_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.35 %
  • code
  • 96.43 %
  • assert
  • 95.79 %
  • func
  • 42.84 %
  • line
  • 99.02 %
  • branch
  • 98.51 %
  • cond
  • 95.41 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.750s 5925.639us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.500s 1055.801us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.340s 439.523us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 64.260s 43587.256us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 884.715us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.170s 586.963us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.340s 439.523us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 884.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 42.160s 161435.118us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 41.270s 164994.736us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 209.110s 482265.617us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 228.320s 496773.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 143.130s 361931.411us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 72.850s 204165.172us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 673.260s 357567.158us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 274.130s 160648.031us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.850s 4152.019us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 37.210s 39763.991us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 46.150s 102360.826us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 196.430s 115927.085us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.640s 488.687us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.950s 406.275us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.220s 686.309us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.220s 686.309us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.500s 1055.801us 1 1 100.00
adc_ctrl_csr_rw 1.340s 439.523us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 884.715us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.100s 4029.969us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.500s 1055.801us 1 1 100.00
adc_ctrl_csr_rw 1.340s 439.523us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 884.715us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.100s 4029.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 12.100s 4559.512us 1 1 100.00
adc_ctrl_tl_intg_err 9.660s 8461.986us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.660s 8461.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.200s 5344.445us 1 1 100.00