| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.770s | 31.700us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.730s | 39.505us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| clkmgr_csr_bit_bash | 6.270s | 1346.861us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 0.920s | 70.181us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.750s | 27.491us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.920s | 70.181us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.760s | 46.711us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.640s | 26.047us | 1 | 1 | 100.00 | |
| extclk | 1 | 1 | 100.00 | |||
| clkmgr_extclk | 0.660s | 15.331us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.660s | 22.961us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.770s | 31.700us | 1 | 1 | 100.00 | |
| frequency | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.380s | 716.834us | 1 | 1 | 100.00 | |
| frequency_timeout | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 10.160s | 2416.381us | 1 | 1 | 100.00 | |
| frequency_overflow | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.380s | 716.834us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| clkmgr_stress_all | 15.890s | 7780.582us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.770s | 46.293us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.450s | 114.360us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.450s | 114.360us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.730s | 39.505us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.920s | 70.181us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 0.870s | 71.262us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.730s | 39.505us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 0.920s | 70.181us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 0.870s | 71.262us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| clkmgr_sec_cm | 1.690s | 192.612us | 1 | 1 | 100.00 | |
| clkmgr_tl_intg_err | 1.730s | 156.628us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.320s | 153.308us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.320s | 153.308us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.320s | 153.308us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.320s | 153.308us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 1.570s | 169.875us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| clkmgr_tl_intg_err | 1.730s | 156.628us | 1 | 1 | 100.00 | |
| sec_cm_meas_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.380s | 716.834us | 1 | 1 | 100.00 | |
| sec_cm_timeout_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 10.160s | 2416.381us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.320s | 153.308us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_idle_intersig_mubi | 1.010s | 163.081us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.740s | 52.422us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 0.710s | 67.749us | 1 | 1 | 100.00 | |
| sec_cm_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 0.680s | 28.688us | 1 | 1 | 100.00 | |
| sec_cm_div_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_div_intersig_mubi | 0.670s | 15.052us | 1 | 1 | 100.00 | |
| sec_cm_jitter_config_mubi | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| sec_cm_idle_ctr_redun | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.690s | 192.612us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| sec_cm_clk_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.810s | 62.333us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.690s | 192.612us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 1 | 1 | 100.00 | |||
| clkmgr_regwen | 2.480s | 736.034us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_stress_all_with_rand_reset | 58.920s | 13570.622us | 1 | 1 | 100.00 | |