Simulation Results: edn

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.50 %
  • code
  • 78.28 %
  • assert
  • 94.22 %
  • func
  • 75.00 %
  • line
  • 96.32 %
  • branch
  • 87.39 %
  • cond
  • 84.25 %
  • toggle
  • 79.27 %
  • FSM
  • 44.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 32.622us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 17.619us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 21.007us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.630s 1002.497us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 87.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 58.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 21.007us 1 1 100.00
edn_csr_aliasing 1.120s 87.957us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.940s 78.360us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.940s 78.360us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.940s 78.360us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 54.221us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 29.856us 1 1 100.00
errs 1 1 100.00
edn_err 0.870s 57.850us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 13.342us 1 1 100.00
edn_disable_auto_req_mode 0.860s 21.153us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.020s 178.231us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 11.475us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 19.823us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.760s 69.850us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.760s 69.850us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 17.619us 1 1 100.00
edn_csr_rw 0.790s 21.007us 1 1 100.00
edn_csr_aliasing 1.120s 87.957us 1 1 100.00
edn_same_csr_outstanding 1.050s 42.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 17.619us 1 1 100.00
edn_csr_rw 0.790s 21.007us 1 1 100.00
edn_csr_aliasing 1.120s 87.957us 1 1 100.00
edn_same_csr_outstanding 1.050s 42.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
edn_tl_intg_err 1.490s 100.348us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 55.147us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 29.856us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 29.856us 1 1 100.00
edn_sec_cm 3.570s 1008.085us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 29.856us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.490s 100.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 83.160s 12534.866us 1 1 100.00