Simulation Results: flash_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 94.45 %
  • assert
  • 96.53 %
  • func
  • 95.82 %
  • line
  • 95.97 %
  • branch
  • 97.15 %
  • cond
  • 94.07 %
  • toggle
  • 97.99 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 21.570s 26.273us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.270s 56.184us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.230s 30.789us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 68.960s 12141.036us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.900s 450.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.170s 234.150us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
flash_ctrl_csr_aliasing 18.900s 450.478us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 11.260s 17.193us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 10.990s 18.898us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.680s 74.473us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 40.870s 220.536us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1226.410s 337579.284us 1 1 100.00
flash_ctrl_hw_rma_reset 550.740s 40129.272us 1 1 100.00
flash_ctrl_lcmgr_intg 5.550s 51.819us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1178.410s 726408.078us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 233.420s 6705.563us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 12.050s 38.083us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2505.190s 649702.225us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 43.530s 403.494us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 19.220s 42.581us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.350s 124.467us 1 1 100.00
flash_ctrl_re_evict 19.850s 224.468us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 99.690s 146.619us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 99.690s 146.619us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 502.930s 62172.900us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.620s 144.720us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 422.140s 2100.234us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 366.370s 2295.420us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 269.150s 614.856us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 881.000s 2227.062us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.770s 41.570us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 115.740s 1462.964us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.260s 94.417us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 9.010s 52.639us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 578.920s 1964.758us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 28.970s 1280.785us 1 1 100.00
flash_ctrl_otp_reset 56.260s 40.348us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1226.410s 337579.284us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 83.190s 3395.092us 1 1 100.00
flash_ctrl_intr_wr 68.400s 32778.602us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 213.880s 25309.581us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 113.700s 20424.878us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 49.190s 879.190us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 36.820s 685.338us 1 1 100.00
double_bit_err 4 5 80.00
flash_ctrl_read_word_sweep_derr 21.060s 202.826us 1 1 100.00
flash_ctrl_ro_derr 94.060s 917.671us 1 1 100.00
flash_ctrl_rw_derr 118.950s 10368.550us 1 1 100.00
flash_ctrl_derr_detect 14.560s 31.452us 0 1 0.00
flash_ctrl_integrity 357.210s 6991.360us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.250s 135.521us 1 1 100.00
flash_ctrl_ro_serr 77.330s 2530.172us 1 1 100.00
flash_ctrl_rw_serr 164.180s 22507.538us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 57.940s 925.970us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 41.280s 2289.281us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 151.400s 3512.835us 1 1 100.00
flash_ctrl_write_word_sweep 12.110s 43.594us 1 1 100.00
flash_ctrl_read_word_sweep 11.570s 47.218us 1 1 100.00
flash_ctrl_ro 76.020s 697.071us 1 1 100.00
flash_ctrl_rw 343.190s 8023.942us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.440s 323.748us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 826.420s 76597.705us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 52.310s 10032.833us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.810s 47.447us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 9.880s 69.890us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.270s 280.138us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.270s 280.138us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.230s 30.789us 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
flash_ctrl_csr_aliasing 18.900s 450.478us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.600s 142.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.230s 30.789us 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
flash_ctrl_csr_aliasing 18.900s 450.478us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.600s 142.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 29.510s 1134.429us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 269.350s 2239.431us 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 269.350s 2239.431us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 269.350s 2239.431us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 12.970s 71.415us 1 1 100.00
flash_ctrl_wr_intg 11.600s 92.201us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 21.570s 26.273us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 56.260s 40.348us 1 1 100.00
flash_ctrl_disable 9.260s 94.417us 1 1 100.00
flash_ctrl_sec_info_access 41.740s 5206.131us 1 1 100.00
flash_ctrl_connect 9.010s 52.639us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.740s 141.856us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.720s 171.765us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.670s 65.789us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.260s 94.417us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 12.970s 71.415us 1 1 100.00
flash_ctrl_access_after_disable 5.560s 94.837us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.560s 40.159us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.260s 94.417us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.620s 144.720us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 343.190s 8023.942us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 164.180s 22507.538us 1 1 100.00
flash_ctrl_rw_derr 118.950s 10368.550us 1 1 100.00
flash_ctrl_integrity 357.210s 6991.360us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1226.410s 337579.284us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.340s 696.409us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.580s 73.000us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.910s 59.535us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1507.510s 9454.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.550s 216.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 28.450s 127.921us 1 1 100.00