Simulation Results: hmac

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.40 %
  • code
  • 97.71 %
  • assert
  • 96.42 %
  • func
  • 44.07 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.420s 1417.241us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.860s 173.710us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 98.181us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.320s 537.157us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.140s 57.196us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.830s 18.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 98.181us 1 1 100.00
hmac_csr_aliasing 2.140s 57.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 13.200s 5528.422us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 28.080s 1804.368us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.150s 271.553us 1 1 100.00
hmac_test_sha384_vectors 433.130s 51105.766us 1 1 100.00
hmac_test_sha512_vectors 19.420s 1378.218us 1 1 100.00
hmac_test_hmac256_vectors 6.670s 412.952us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1254.274us 1 1 100.00
hmac_test_hmac512_vectors 9.540s 261.664us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.870s 1929.475us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 378.350s 12058.124us 1 1 100.00
error 1 1 100.00
hmac_error 39.650s 15522.535us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 79.580s 2507.282us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.420s 1417.241us 1 1 100.00
hmac_long_msg 13.200s 5528.422us 1 1 100.00
hmac_back_pressure 28.080s 1804.368us 1 1 100.00
hmac_datapath_stress 378.350s 12058.124us 1 1 100.00
hmac_burst_wr 13.870s 1929.475us 1 1 100.00
hmac_stress_all 1116.790s 22517.752us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.420s 1417.241us 1 1 100.00
hmac_long_msg 13.200s 5528.422us 1 1 100.00
hmac_back_pressure 28.080s 1804.368us 1 1 100.00
hmac_datapath_stress 378.350s 12058.124us 1 1 100.00
hmac_wipe_secret 79.580s 2507.282us 1 1 100.00
hmac_test_sha256_vectors 8.150s 271.553us 1 1 100.00
hmac_test_sha384_vectors 433.130s 51105.766us 1 1 100.00
hmac_test_sha512_vectors 19.420s 1378.218us 1 1 100.00
hmac_test_hmac256_vectors 6.670s 412.952us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1254.274us 1 1 100.00
hmac_test_hmac512_vectors 9.540s 261.664us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.420s 1417.241us 1 1 100.00
hmac_long_msg 13.200s 5528.422us 1 1 100.00
hmac_back_pressure 28.080s 1804.368us 1 1 100.00
hmac_datapath_stress 378.350s 12058.124us 1 1 100.00
hmac_burst_wr 13.870s 1929.475us 1 1 100.00
hmac_error 39.650s 15522.535us 1 1 100.00
hmac_wipe_secret 79.580s 2507.282us 1 1 100.00
hmac_test_sha256_vectors 8.150s 271.553us 1 1 100.00
hmac_test_sha384_vectors 433.130s 51105.766us 1 1 100.00
hmac_test_sha512_vectors 19.420s 1378.218us 1 1 100.00
hmac_test_hmac256_vectors 6.670s 412.952us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1254.274us 1 1 100.00
hmac_test_hmac512_vectors 9.540s 261.664us 1 1 100.00
hmac_stress_all 1116.790s 22517.752us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1116.790s 22517.752us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 15.255us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.570s 44.985us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.100s 93.529us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.100s 93.529us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.860s 173.710us 1 1 100.00
hmac_csr_rw 0.830s 98.181us 1 1 100.00
hmac_csr_aliasing 2.140s 57.196us 1 1 100.00
hmac_same_csr_outstanding 1.630s 46.695us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.860s 173.710us 1 1 100.00
hmac_csr_rw 0.830s 98.181us 1 1 100.00
hmac_csr_aliasing 2.140s 57.196us 1 1 100.00
hmac_same_csr_outstanding 1.630s 46.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.130s 90.858us 1 1 100.00
hmac_tl_intg_err 3.320s 3296.747us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.320s 3296.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.420s 1417.241us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.380s 259.988us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 106.990s 8611.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.850s 8.801us 1 1 100.00