Simulation Results: i2c

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.43 %
  • code
  • 81.29 %
  • assert
  • 95.77 %
  • func
  • 82.24 %
  • line
  • 96.38 %
  • branch
  • 92.19 %
  • cond
  • 84.97 %
  • toggle
  • 89.45 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 22.540s 1989.062us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 18.740s 3178.339us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.720s 41.038us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.900s 82.995us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.470s 229.312us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.190s 55.732us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.070s 35.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.900s 82.995us 1 1 100.00
i2c_csr_aliasing 1.190s 55.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.030s 14.756us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 84.930s 7479.187us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 954.120s 26725.095us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.970s 30.303us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 74.990s 21339.295us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 115.630s 4956.830us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.460s 648.145us 1 1 100.00
i2c_host_fifo_fmt_empty 6.850s 2620.697us 1 1 100.00
i2c_host_fifo_reset_rx 2.540s 132.507us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 33.860s 2048.069us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.720s 1573.615us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 3.030s 166.252us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.350s 1660.226us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 37.080s 40648.017us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.390s 2902.508us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 17.350s 1320.524us 1 1 100.00
i2c_target_intr_smoke 4.060s 1880.569us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.940s 216.864us 1 1 100.00
i2c_target_fifo_reset_tx 0.940s 235.771us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 1082.290s 64995.490us 1 1 100.00
i2c_target_stress_rd 17.350s 1320.524us 1 1 100.00
i2c_target_intr_stress_wr 55.760s 31039.025us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.760s 2705.398us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 22.460s 2325.423us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.250s 1140.167us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.100s 305.591us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.010s 345.172us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.190s 236.282us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 954.120s 26725.095us 1 1 100.00
i2c_host_perf_precise 4.460s 234.168us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.720s 1573.615us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.760s 161.393us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.890s 2017.943us 1 1 100.00
i2c_target_nack_acqfull_addr 1.970s 3758.423us 1 1 100.00
i2c_target_nack_txstretch 1.240s 854.972us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 12.770s 450.618us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.920s 787.076us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.740s 98.902us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.730s 22.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.270s 95.228us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.270s 95.228us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.720s 41.038us 1 1 100.00
i2c_csr_rw 0.900s 82.995us 1 1 100.00
i2c_csr_aliasing 1.190s 55.732us 1 1 100.00
i2c_same_csr_outstanding 1.180s 253.293us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.720s 41.038us 1 1 100.00
i2c_csr_rw 0.900s 82.995us 1 1 100.00
i2c_csr_aliasing 1.190s 55.732us 1 1 100.00
i2c_same_csr_outstanding 1.180s 253.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.580s 172.826us 1 1 100.00
i2c_sec_cm 0.970s 281.026us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.580s 172.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 9.750s 864.324us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.160s 308.036us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 8.040s 2777.459us 0 1 0.00