Simulation Results: lc_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.98 %
  • code
  • 83.30 %
  • assert
  • 94.13 %
  • func
  • 89.50 %
  • line
  • 97.08 %
  • branch
  • 93.51 %
  • cond
  • 78.67 %
  • toggle
  • 73.82 %
  • FSM
  • 73.40 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.800s 91.298us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.870s 42.890us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.857us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 47.375us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 28.607us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 124.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 16.857us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 28.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 2.880s 7.635us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.370s 611.563us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 13.171us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.090s 343.830us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.780s 428.887us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_prog_failure 2.090s 343.830us 1 1 100.00
lc_ctrl_errors 3.780s 428.887us 1 1 100.00
lc_ctrl_security_escalation 6.180s 1021.322us 1 1 100.00
lc_ctrl_jtag_state_failure 7.320s 1675.397us 0 1 0.00
lc_ctrl_jtag_prog_failure 12.320s 2665.453us 1 1 100.00
lc_ctrl_jtag_errors 20.550s 2206.515us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.620s 862.969us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.360s 809.761us 1 1 100.00
lc_ctrl_jtag_prog_failure 12.320s 2665.453us 1 1 100.00
lc_ctrl_jtag_errors 20.550s 2206.515us 1 1 100.00
lc_ctrl_jtag_access 5.200s 292.074us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.290s 979.283us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.220s 73.734us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.530s 377.710us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.820s 741.126us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.560s 1336.207us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 16.131us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.260s 69.052us 1 1 100.00
lc_ctrl_jtag_alert_test 1.210s 136.355us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.780s 933.099us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 45.951us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 14.310s 973.001us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.870s 60.356us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 141.759us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 141.759us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 42.890us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.857us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 28.607us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 96.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 42.890us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.857us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 28.607us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.070s 96.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 582.823us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 582.823us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.370s 611.563us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.110s 7.703us 0 1 0.00
lc_ctrl_sec_cm 5.440s 255.118us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.180s 1021.322us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.880s 7.635us 0 1 0.00
lc_ctrl_jtag_state_post_trans 9.360s 809.761us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.640s 333.314us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.640s 333.314us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.830s 328.973us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.270s 169.230us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.270s 169.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.590s 15.704us 0 1 0.00