Simulation Results: lc_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.37 %
  • code
  • 83.98 %
  • assert
  • 94.13 %
  • func
  • 87.01 %
  • line
  • 97.11 %
  • branch
  • 93.92 %
  • cond
  • 79.14 %
  • toggle
  • 81.31 %
  • FSM
  • 68.42 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.700s 259.129us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.220s 70.335us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.050s 50.158us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.170s 146.394us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 81.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.220s 76.792us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.050s 50.158us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 81.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.460s 30.002us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.790s 690.026us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 38.419us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.960s 326.587us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.330s 581.285us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_prog_failure 1.960s 326.587us 1 1 100.00
lc_ctrl_errors 7.330s 581.285us 1 1 100.00
lc_ctrl_security_escalation 4.470s 467.422us 1 1 100.00
lc_ctrl_jtag_state_failure 3.880s 1024.810us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.910s 3925.623us 1 1 100.00
lc_ctrl_jtag_errors 24.520s 2415.996us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 8.580s 535.390us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.810s 2925.344us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.910s 3925.623us 1 1 100.00
lc_ctrl_jtag_errors 24.520s 2415.996us 1 1 100.00
lc_ctrl_jtag_access 13.670s 1262.862us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 25.060s 4647.275us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.140s 54.990us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.940s 48.234us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.210s 5203.621us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.630s 1472.544us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.200s 26.150us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.550s 87.213us 1 1 100.00
lc_ctrl_jtag_alert_test 1.280s 98.174us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.060s 1526.247us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.950s 19.155us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 3.330s 350.560us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.070s 17.207us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.870s 211.832us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.870s 211.832us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.220s 70.335us 1 1 100.00
lc_ctrl_csr_rw 1.050s 50.158us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 81.400us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 148.952us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.220s 70.335us 1 1 100.00
lc_ctrl_csr_rw 1.050s 50.158us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 81.400us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 148.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
lc_ctrl_tl_intg_err 2.290s 444.008us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.290s 444.008us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.790s 690.026us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.210s 6.178us 0 1 0.00
lc_ctrl_sec_cm 6.600s 232.977us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.470s 467.422us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.460s 30.002us 0 1 0.00
lc_ctrl_jtag_state_post_trans 4.810s 2925.344us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 1201.055us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 1201.055us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.180s 695.917us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.910s 346.191us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.910s 346.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.130s 9361.039us 1 1 100.00