Simulation Results: pattgen

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 113.688us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 57.192us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 36.924us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 651.402us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 130.718us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 20.159us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 36.924us 1 1 100.00
pattgen_csr_aliasing 2.000s 130.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 791.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 10.000s 5488.915us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 274.402us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 109.797us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 14.763us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 15.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 85.794us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 85.794us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 57.192us 1 1 100.00
pattgen_csr_rw 2.000s 36.924us 1 1 100.00
pattgen_csr_aliasing 2.000s 130.718us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 108.288us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 57.192us 1 1 100.00
pattgen_csr_rw 2.000s 36.924us 1 1 100.00
pattgen_csr_aliasing 2.000s 130.718us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 108.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 2.000s 234.884us 1 1 100.00
pattgen_tl_intg_err 2.000s 217.948us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 217.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 67.000s 5109.423us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 74.097us 1 1 100.00