| V1 |
|
100.00% |
| V2 |
|
95.83% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwm_smoke | 3.000s | 2207.315us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 85.595us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwm_csr_rw | 2.000s | 21.341us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwm_csr_bit_bash | 5.000s | 577.321us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwm_csr_aliasing | 2.000s | 35.664us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwm_csr_mem_rw_with_rand_reset | 2.000s | 112.568us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwm_csr_rw | 2.000s | 21.341us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 35.664us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dutycycle | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| pulse | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| blink | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| heartbeat | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| resolution | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| multi_channel | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| polarity | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| phase | 2 | 2 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| pwm_phase | 32.000s | 52505.305us | 1 | 1 | 100.00 | |
| lowpower | 1 | 1 | 100.00 | |||
| pwm_rand_output | 28.000s | 51583.996us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| pwm_perf | 23.000s | 10718.911us | 1 | 1 | 100.00 | |
| regwen | 0 | 1 | 0.00 | |||
| pwm_regwen | 274.000s | 10929.612us | 0 | 1 | 0.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| pwm_stress_all | 146.000s | 42588.894us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| pwm_alert_test | 1.000s | 13.614us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 3.000s | 94.363us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 3.000s | 94.363us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 85.595us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 21.341us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 35.664us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 26.407us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 2.000s | 85.595us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 21.341us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 35.664us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 26.407us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| pwm_sec_cm | 1.000s | 74.249us | 1 | 1 | 100.00 | |
| pwm_tl_intg_err | 2.000s | 102.118us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| pwm_tl_intg_err | 2.000s | 102.118us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| heartbeat_wrap | 1 | 1 | 100.00 | |||
| pwm_heartbeat_wrap | 34.000s | 22340.342us | 1 | 1 | 100.00 | |