Simulation Results: pwrmgr

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 94.48 %
  • assert
  • 96.08 %
  • func
  • 96.54 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.06 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.650s 23.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.620s 229.307us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.350s 543.056us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.850s 23.229us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.680s 69.762us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 23.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.650s 63.526us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.650s 63.526us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 38.997us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 42.462us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.730s 72.800us 1 1 100.00
pwrmgr_reset_invalid 0.880s 110.854us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.730s 72.800us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 120.703us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.040s 322.054us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.840s 99.737us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.860s 555.008us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.570s 45.157us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.760s 178.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.760s 178.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 229.307us 1 1 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 23.229us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 24.646us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 229.307us 1 1 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 23.229us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 24.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
pwrmgr_tl_intg_err 0.580s 12.841us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.580s 12.841us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.610s 1227.929us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.680s 120.703us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.740s 134.164us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.620s 39.124us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.650s 37.430us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 69.676us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.720s 44.223us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.700s 64.429us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 56.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.750s 180.307us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.840s 4072.033us 1 1 100.00