Simulation Results: rom_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.88 %
  • code
  • 98.49 %
  • assert
  • 95.49 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 94.50 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.960s 276.102us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.840s 1036.828us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.870s 2505.578us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.110s 292.497us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 1116.741us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.720s 735.650us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.870s 2505.578us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 1116.741us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.470s 392.914us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.420s 1071.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.770s 387.234us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 27.470s 804.469us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.180s 558.650us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.740s 641.160us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.560s 580.568us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.560s 580.568us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.840s 1036.828us 1 1 100.00
rom_ctrl_csr_rw 6.870s 2505.578us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 1116.741us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.120s 791.585us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.840s 1036.828us 1 1 100.00
rom_ctrl_csr_rw 6.870s 2505.578us 1 1 100.00
rom_ctrl_csr_aliasing 6.540s 1116.741us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.120s 791.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.850s 1090.801us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
rom_ctrl_tl_intg_err 49.980s 1251.450us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.960s 276.102us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.960s 276.102us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.960s 276.102us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.980s 1251.450us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
rom_ctrl_kmac_err_chk 14.180s 558.650us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.230s 9441.559us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.850s 1090.801us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 232.540s 1052.865us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 69.170s 12450.049us 1 1 100.00