Simulation Results: rstmgr

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 99.39 %
  • assert
  • 97.99 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.270s 205.196us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.830s 86.737us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.340s 470.747us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.220s 115.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.170s 110.327us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00
rstmgr_csr_aliasing 1.220s 115.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.980s 141.456us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.310s 124.614us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.260s 289.197us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.460s 1584.337us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.460s 1584.337us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.460s 1584.337us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.460s 1584.337us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 7.330s 2437.295us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.960s 67.744us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.440s 437.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.440s 437.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.830s 86.737us 1 1 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00
rstmgr_csr_aliasing 1.220s 115.992us 1 1 100.00
rstmgr_same_csr_outstanding 1.240s 134.991us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.830s 86.737us 1 1 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00
rstmgr_csr_aliasing 1.220s 115.992us 1 1 100.00
rstmgr_same_csr_outstanding 1.240s 134.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 13.520s 8434.716us 1 1 100.00
rstmgr_tl_intg_err 1.810s 492.501us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 13.520s 8434.716us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 13.520s 8434.716us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.810s 492.501us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.990s 141.530us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.730s 2443.142us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.250s 301.653us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 13.520s 8434.716us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 74.864us 1 1 100.00