Simulation Results: spi_device

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.38 %
  • code
  • 93.23 %
  • assert
  • 94.03 %
  • func
  • 71.88 %
  • line
  • 99.10 %
  • branch
  • 98.37 %
  • cond
  • 95.77 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 51.640s 39057.632us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.080s 164.012us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.440s 72.076us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.810s 188.388us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.440s 212.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.920s 150.600us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.440s 72.076us 1 1 100.00
spi_device_csr_aliasing 9.440s 212.091us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 44.132us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.620s 40.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.920s 64.654us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.650s 1.065us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.720s 3.263us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.790s 168.377us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.790s 168.377us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.430s 3085.083us 1 1 100.00
spi_device_tpm_sts_read 0.760s 124.956us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 10.300s 5155.021us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 11.150s 10633.786us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 4275.581us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 4275.581us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.390s 212.400us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.390s 212.400us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.390s 212.400us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.390s 212.400us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.390s 212.400us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.540s 748.773us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.000s 686.574us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.000s 686.574us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.000s 686.574us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 17.110s 2399.887us 1 1 100.00
spi_device_read_buffer_direct 3.380s 855.624us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.000s 686.574us 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 17.470s 1647.232us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.780s 1925.319us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.780s 1925.319us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 51.640s 39057.632us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 19.220s 1301.887us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 286.920s 50129.728us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 25.868us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 11.705us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.790s 711.048us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.790s 711.048us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 164.012us 1 1 100.00
spi_device_csr_rw 1.440s 72.076us 1 1 100.00
spi_device_csr_aliasing 9.440s 212.091us 1 1 100.00
spi_device_same_csr_outstanding 1.360s 54.177us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 164.012us 1 1 100.00
spi_device_csr_rw 1.440s 72.076us 1 1 100.00
spi_device_csr_aliasing 9.440s 212.091us 1 1 100.00
spi_device_same_csr_outstanding 1.360s 54.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 5.330s 565.488us 1 1 100.00
spi_device_sec_cm 1.080s 253.686us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.330s 565.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 33.540s 3967.715us 1 1 100.00