Simulation Results: spi_host

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.16 %
  • code
  • 95.02 %
  • assert
  • 93.54 %
  • func
  • 87.92 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 662.035us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 31.909us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 38.432us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 445.666us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 22.679us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 65.856us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 38.432us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.679us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.526us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 48.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 5.000s 40.534us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 8.000s 611.874us 1 1 100.00
spi_host_error_cmd 3.000s 82.522us 1 1 100.00
spi_host_event 6.000s 3375.055us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 7.000s 69.576us 1 1 100.00
speed 1 1 100.00
spi_host_speed 7.000s 69.576us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 7.000s 69.576us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 123.116us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 31.577us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 7.000s 69.576us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 7.000s 69.576us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 662.035us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 662.035us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 65.000s 15683.555us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 684.042us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 55.000s 1797.502us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 119.546us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 8.000s 611.874us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 103.671us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 972.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 972.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 31.909us 1 1 100.00
spi_host_csr_rw 2.000s 38.432us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.679us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 62.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 31.909us 1 1 100.00
spi_host_csr_rw 2.000s 38.432us 1 1 100.00
spi_host_csr_aliasing 1.000s 22.679us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 62.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 172.917us 1 1 100.00
spi_host_tl_intg_err 2.000s 97.508us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 97.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 204.000s 26648.745us 1 1 100.00