Simulation Results: sram_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.64 %
  • code
  • 90.38 %
  • assert
  • 95.55 %
  • func
  • 94.99 %
  • line
  • 97.77 %
  • branch
  • 95.79 %
  • cond
  • 91.43 %
  • toggle
  • 90.71 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 43.480s 889.704us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 42.811us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.790s 15.221us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.440s 47.356us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 55.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.250s 361.415us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.790s 15.221us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 55.139us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 137.220s 22475.841us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.800s 960.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 212.870s 8896.471us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 170.910s 5105.044us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 726.340s 15074.874us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 310.890s 6743.476us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 60.140s 16389.222us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 668.430s 113930.160us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 61.190s 830.090us 1 1 100.00
sram_ctrl_partial_access_b2b 152.640s 9313.007us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 9.670s 1746.357us 1 1 100.00
sram_ctrl_throughput_w_partial_write 11.900s 1494.590us 1 1 100.00
sram_ctrl_throughput_w_readback 75.930s 7604.101us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 531.550s 5650.276us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.220s 1775.355us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2008.010s 122813.229us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.900s 13.207us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.140s 150.778us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.140s 150.778us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 42.811us 1 1 100.00
sram_ctrl_csr_rw 0.790s 15.221us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 55.139us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 28.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 42.811us 1 1 100.00
sram_ctrl_csr_rw 0.790s 15.221us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 55.139us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 28.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 35.340s 7352.798us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.410s 283.185us 1 1 100.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.410s 283.185us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 531.550s 5650.276us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 531.550s 5650.276us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.790s 15.221us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 668.430s 113930.160us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 668.430s 113930.160us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 668.430s 113930.160us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 60.140s 16389.222us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 7.600s 680.076us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 35.340s 7352.798us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.400s 2639.765us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 43.480s 889.704us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 43.480s 889.704us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 668.430s 113930.160us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 60.140s 16389.222us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 43.480s 889.704us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.770s 10.956us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 2197.547us 1 1 100.00