Simulation Results: sram_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 96.07 %
  • assert
  • 95.79 %
  • func
  • 94.81 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.66 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
90.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 52.260s 763.025us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 18.590us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.760s 36.874us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.640s 124.732us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 24.061us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.500s 88.337us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.760s 36.874us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 24.061us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.490s 1122.658us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.650s 343.037us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 167.170s 10317.408us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 92.630s 11950.837us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 11.810s 496.883us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 293.950s 5371.035us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.530s 782.378us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 440.440s 32002.234us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 33.000s 2033.302us 1 1 100.00
sram_ctrl_partial_access_b2b 262.840s 15264.640us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 19.720s 365.487us 1 1 100.00
sram_ctrl_throughput_w_partial_write 54.140s 1329.767us 1 1 100.00
sram_ctrl_throughput_w_readback 8.800s 818.680us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 517.100s 57728.078us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.980s 25.864us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1326.140s 230083.336us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.720s 24.945us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.540s 970.623us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.540s 970.623us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 18.590us 1 1 100.00
sram_ctrl_csr_rw 0.760s 36.874us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 24.061us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 27.107us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 18.590us 1 1 100.00
sram_ctrl_csr_rw 0.760s 36.874us 1 1 100.00
sram_ctrl_csr_aliasing 0.740s 24.061us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 27.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.470s 391.721us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.360s 129.861us 1 1 100.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.360s 129.861us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 517.100s 57728.078us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 517.100s 57728.078us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.760s 36.874us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 440.440s 32002.234us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 440.440s 32002.234us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 440.440s 32002.234us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.530s 782.378us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.840s 41.183us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.470s 391.721us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.900s 191.425us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 52.260s 763.025us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 52.260s 763.025us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 440.440s 32002.234us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.530s 782.378us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 52.260s 763.025us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.177us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 123.710s 2464.180us 1 1 100.00