Simulation Results: sysrst_ctrl

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.15 %
  • code
  • 89.14 %
  • assert
  • 87.74 %
  • func
  • 57.56 %
  • line
  • 95.11 %
  • branch
  • 96.00 %
  • cond
  • 92.12 %
  • toggle
  • 99.66 %
  • FSM
  • 62.82 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.410s 2114.977us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.080s 2511.038us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.840s 2288.287us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.870s 2538.592us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.000s 6021.664us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.490s 2039.094us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 15.090s 4749.788us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2705.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.710s 2067.325us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.490s 2039.094us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2705.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 200.000s 115674.618us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 22.290s 24838.978us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.170s 3275.278us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 9.320s 5592.278us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.870s 2524.614us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.190s 2194.993us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1172.130s 1144356.821us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.000s 2634.314us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 4.440s 5131.064us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 38.660s 40654.219us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.820s 12646.184us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.650s 2012.597us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.070s 2047.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.050s 2092.458us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.050s 2092.458us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.000s 6021.664us 1 1 100.00
sysrst_ctrl_csr_rw 4.490s 2039.094us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2705.910us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.270s 7378.186us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.000s 6021.664us 1 1 100.00
sysrst_ctrl_csr_rw 4.490s 2039.094us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2705.910us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.270s 7378.186us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.240s 22087.325us 1 1 100.00
sysrst_ctrl_tl_intg_err 38.440s 22219.774us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 38.440s 22219.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.640s 4752.163us 1 1 100.00