Simulation Results: uart

 
04/12/2025 17:27:49 sha: 45431ee json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.72 %
  • code
  • 96.19 %
  • assert
  • 97.12 %
  • func
  • 51.84 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.85 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.430s 677.595us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 44.835us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 49.338us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.700s 229.122us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.750s 40.682us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.780s 210.486us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 49.338us 1 1 100.00
uart_csr_aliasing 0.750s 40.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 1.360s 2104.050us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.430s 677.595us 1 1 100.00
uart_tx_rx 1.360s 2104.050us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.240s 14169.274us 1 1 100.00
uart_rx_parity_err 159.640s 135792.892us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 1.360s 2104.050us 1 1 100.00
uart_intr 4.240s 14169.274us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 142.780s 184891.924us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 32.630s 138195.214us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 94.990s 226953.430us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.240s 14169.274us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.240s 14169.274us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.240s 14169.274us 1 1 100.00
perf 1 1 100.00
uart_perf 67.440s 25417.282us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.530s 10615.817us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.530s 10615.817us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 7.150s 19518.708us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 11.440s 45243.779us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.240s 928.060us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.590s 2015.841us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 650.270s 112202.832us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 24.760s 116465.641us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.700s 28.197us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.780s 15.478us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.190s 36.041us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.190s 36.041us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 44.835us 1 1 100.00
uart_csr_rw 0.620s 49.338us 1 1 100.00
uart_csr_aliasing 0.750s 40.682us 1 1 100.00
uart_same_csr_outstanding 0.790s 32.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 44.835us 1 1 100.00
uart_csr_rw 0.620s 49.338us 1 1 100.00
uart_csr_aliasing 0.750s 40.682us 1 1 100.00
uart_same_csr_outstanding 0.790s 32.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.360s 282.819us 1 1 100.00
uart_sec_cm 1.180s 72.587us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.360s 282.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.540s 4577.394us 1 1 100.00