Simulation Results: adc_ctrl

 
08/12/2025 17:17:43 sha: cbcfe8e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.99 %
  • code
  • 96.90 %
  • assert
  • 95.79 %
  • func
  • 44.27 %
  • line
  • 99.05 %
  • branch
  • 98.58 %
  • cond
  • 95.00 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.790s 6181.133us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.360s 853.575us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.650s 499.601us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 7.790s 26033.428us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 5.110s 1111.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.610s 393.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.650s 499.601us 1 1 100.00
adc_ctrl_csr_aliasing 5.110s 1111.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 70.450s 319972.776us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 417.460s 493246.823us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 174.130s 493913.462us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 70.150s 166615.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 415.080s 521654.369us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 173.230s 398860.055us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 259.960s 163963.321us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 211.380s 164563.631us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 14.150s 4402.815us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 15.170s 33102.590us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 38.650s 88971.457us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 113.550s 236125.984us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.260s 283.356us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.970s 406.594us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.950s 444.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.950s 444.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.360s 853.575us 1 1 100.00
adc_ctrl_csr_rw 1.650s 499.601us 1 1 100.00
adc_ctrl_csr_aliasing 5.110s 1111.497us 1 1 100.00
adc_ctrl_same_csr_outstanding 14.500s 4600.234us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.360s 853.575us 1 1 100.00
adc_ctrl_csr_rw 1.650s 499.601us 1 1 100.00
adc_ctrl_csr_aliasing 5.110s 1111.497us 1 1 100.00
adc_ctrl_same_csr_outstanding 14.500s 4600.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 14.800s 7683.203us 1 1 100.00
adc_ctrl_tl_intg_err 8.710s 4391.961us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.710s 4391.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.700s 17450.390us 1 1 100.00

Error Messages

   Test seed line log context